1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to scan testing of integrated circuits.
2. Description of the Related Art
Subsequent to manufacture and prior to shipping, integrated circuits (IC's) may be tested to verify their functionality. One type of testing that may be conducted is known as scan testing. To conduct a scan test, test stimulus data may be input into an IC through a serially coupled chain of scannable elements. Each scannable element may include a data input, a scan data input, a data output, and a scan data output. The scan data output of all but the last scannable element may be coupled to the scan data input of a next scannable element. Test stimulus data may be shifted into each scannable element through its scan data input, and applied to logic circuitry (e.g., combinational logic) via its data output. Test stimulus data may be applied to the logic circuitry responsive to a first cycle of a clock signal, sometimes referred to as a launch cycle. Test result data may be captured responsive to a second cycle of the clock signal (sometimes referred to as a capture cycle) on the data input of the scannable element. Subsequent to capture, the test result data may be shifted through the scan chain via the scan data input and scan data output of each scan chain.
Using scan testing, different types of tests may be conducted. One type of testing is known as transition testing, which may test whether the outputs of certain logic circuits may make a logical transition, either from a logic 0 to a logic 1, from a logic 1 to a logic 0, or both. Some delay tests, such as transition delay fault tests, may require the application of test stimulus data for two or more consecutive clock cycles at an operational clock speed in order to ensure that both logical transitions may occur as intended.
Many IC's include one or more memory arrays. The read ports of some of these memory arrays may be coupled to the data input of each of a number of scannable elements. However, the data stored in the memory arrays during scan testing is typically indeterminate. Because of this arrangement, transition testing of combinational logic circuitry coupled to the output of such scannable elements may require bypass circuitry. Bypass circuitry may be implemented using a multiplexer coupled to the data input of such scannable elements. This may in turn enable at-speed transition testing of scannable elements having data inputs that are otherwise coupled to read port outputs of a memory array, as the read port outputs may be bypassed by selecting the output of another scannable element coupled to the multiplexer. These multiplexers introduce additional circuitry that may add delay to the path between the read port output and the scannable elements.